Friday 7 August 2015

VHDL testbench template generator

This page generates a VHDL testbench template (which is equivalent to a partial testbench), based on the entity declaration of the component that is to be the Unit Under Test (UUT). The entity name of the testbench is formed by adding the suffix "_tb" to the entity name of the UUT module.

The aim of the testbench template generator is to take out some of the drudgery associated with creating a VHDL testbench of a design, especially when there are lots of ports for that design. Naturally, the testbench needs to be completed and modified by the user as appropriate.

An example input entity listing already occurs in the input textarea. Note that the closing brackets for the generic and port must be on separate lines for the generator to work.

The testbench template generator detects any input signal which is a clock (the clock signal name should contain either the string "clk" or "clock") and creates constant declarations for the clock periods, as well as logic for generating the clocks in the body of the test bench.

For generics of the UUT, thse are declared as constants and must be assigned with a value - please replace the placeholder INSERT VALUE HERE with the desired value.



Input Entity Declaration







Generated Testbench

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